This application is based on and claims the benefit of priority from the prior Japanese Patent Application No. 2000-304003, filed on Oct. 3, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to non-volatile semiconductor memory devices.
2. Description of the Related Art
Currently available large-scale semiconductor memory devices are typically designed to come with built-in redundancy circuitry which permits relieving the device including defects, if any. The same goes with electrically erasable programmable read-only memory (EEPROM) chips. With standard redundancy circuit designs, a redundant row cell array and redundant column cell array are provided in addition to an ordinary or standard cell array. Also provided is fuse circuitry which stores therein defect addresses and detects whether an externally supplied address coincides with the presently stored defect address for controlling address replacement or substitution. The fuse circuitry is typically designed to employ an array of laser-blown type fuses.
The fuse circuit is also used to write or xe2x80x9cprogramxe2x80x9d a variety of kinds of initial setup data for determination of the operating conditions of a memory chip, in addition to defect address data for defect repairing purposes. Examples of such initial setup data include, but not limited to, data for adjustment of voltages as internally produced on a chip in accordance with fabrication process parameter irregularities, setup data of a write voltage(s), and control parameters of the requisite number of write/erase control loops.
Unfortunately, the fuse circuit lacks functional flexibilities due to the fact that it will hardly permit any re-programming once after having programmed in a certain way. Another disadvantage is that extraction of defective portions through a test at the stage of wafer test/inspection and laser blowout process must be done separately at different process steps. Additionally these are hardly implementable as a series of continuous steps.
A currently proposed approach to avoiding the problems is to employ as an initial setup data storage circuit in place of the fuse elements an array of electrically rewritable non-volatile memory cells which are the same as those used in EEPROMs. Employing such non-volatile memory cells makes data writing easier when compared to traditional fuse blowout techniques, while enabling establishment of rewriting or xe2x80x9creprogrammingxe2x80x9d of the data.
However, one prior known scheme is for disposing the non-volatile memory cell array for storage of the initial setup data in a specific region that is kept separate from a xe2x80x9cmainxe2x80x9d memory cell array. With this scheme, storing initial setup data does require the use of separate or xe2x80x9cextraxe2x80x9d rewrite/read circuitry in addition to the main memory cell array""s inherent rewrite/read circuitry, which would result in an increase in complexity of circuit configuration while increasing the resultant chip area. Another problem faced with the prior art is the difficulty in operation control procedure due to the necessity of verification and correction after once having written the initial setup data.
The non-volatile semiconductor memory device in accordance with one aspect of the invention includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.